Table of Contents
Architecture of 8086 microprocessor
A microprocessor is an Integrated circuit with all the functions of CPUI like controlling all the commands. 8086 does not have any ROM or RAM inside it. It has an internal register for storing intermediate and final results and it interfaces with memory located outside it through the system bus.
The 8086 microprocessor has its own internal architecture which is divided into two units:-
- The Bus Interfacing Unit (BIU)
- The Execution Unit (EU)
Bus interfacing unit (BIU)
Before Knowing more about the bus interface unit we must know what the bus is. Therefore, the bus is a type of conductor. Or we can see wires that are available at the microprocessor, which are useful to conduct data transmission, information control and perform addressed tasks.
The BIU unit provides an Interface or communicates between 8086 to external memory and I/O devices via a system bus. Basically, it reads the memory instructions To transfer the data between memory and input-output devices. It also maintains 6 Byte prefetch or we can say preloaded instruction queues.
The bus interface unit includes the following elements :
- Instruction queue: The 8086 microprocessor has a 6-byte queue which works on the first-in-first-out format. It can load the next instruction (by BIU from CS, where the program is stored) while executing the current instruction. It is a pipelining method. There is a gap between every 6-byte queue, which is 2-byte
- Segment Registers: The following are some internal registers available at 8086 that are used to store or hold the base address
- Code segment register (CS): It addresses the memory of the code segment to store the executable program
- Data segment register (DS): It consists of the data which can be accessed by the program
- Stack segment register (SS): It handles the memory storing data and addresses during the execution of the program
- Extra segment register (ES): It is an additional data segment that is used to hold the extra data.
- Instruction pointer (IP): It is a 16-bit register. It holds the address of the next instruction, which is going to be executed
The execution unit
As the name itself says, this unit executes the operation while getting the instructions from the 6-byte queue. It gets the instruction from the queue in BIU, decodes the Opcode, and executes the arithmetic and logical operations. It sends request signals to BIU to get instructions to perform operations and access the external models which are connected externally
The execution unit includes the following elements :
- Control System: The control System generates control signals and converts opcodes From the queue, converts, and executes the arithmetic and logic functions.
- ALU ( Arithmetic and Logical Unit): Arithmetic and Logical Unit performs arithmetic operations & also logical operations. (16-bit and 8-bit) e.g. Add, sub, mul, div, ANL, OR.
- The General Purpose Registers: 8086 has 16-bit general purpose registers Ax, Bx, CX, and DX. They store the intermediate values during execution. If you are performing any two operations and the result you can store it at any general purpose register temporarily during the execution of another operation. These 4 16-bit registers are divided into 8-bit :
- AX registers: It holds operands and. Result during multiplication & division operations.
- BX registers: It holds memory addresses in indirect addressing modes.
- CX registers: It holds the count for instructions like a loop, rotate shift string operation.
- DX registers: It is used with AX to bald 32-bit values during multiplication & division.
- Flag/Status Register (16-bit):
There are a total of 9 flags in 8086 and the whole flag register is divided into two types:
- Status Flags:
There are six status flag registers in the 8086 microprocessor. They will set (1) or reset (0), depending upon conditions after either 8-bit or 16-bit operation. The 6 conditional flags are:-
- The parity flags(PF):- This flag will be set to 1 if the result has even parity i.e. even parity = 1 (LSB byte). Also, this flag will be set to 0 if the result has odd parity i.e. odd parity = 0 (LSB byte).
- The carry flags(CF):- It is also called final carry. This carry is set to 1 if there is carry out or borrow into the most significant bit (MSB) of the result (either 8 or 16 bit).
- CF=1; if carry generates
- CF=0; if carry does not generate
- The Auxillary carry flags(AF):- If carry is generated from the lower nibble to the higher nibble the AF=1, if no carry is generated then AF=0
- The zero flags(ZF):- The zero flags will be set to 1 if the result is zero else it will be 0 if the result is non-zero.
- ZF=1; if the result is zero
- ZF=0; if the result is non-zero
- The sign flags(SF):- Sign flags will be set to 1 when the MSB of the result is 1 or positive. If the result is 0 or negative it will set to 0.
- SF=1; if the result has MSB 1 or positive
- SF=2; if the result has MSB 0 or negative
- The overflow flag(OF):- This flag indicates an overflow from magnitude to sign bit of result. Also if carry is generating from the 6th bit to the 7th beat, OF=zero. If there is no carry from 6 bit to the seventh bit, OF= zero.
- OF=1; Signed overflow occurred.
- OF=0; No signed overflow occurred.
- Control Flags:- Control flags are used to control certain operations of the processor.
- The tarp flags(TF):- When TF=1, it puts the processor into a single-step mode for debugging therefore, the trap is on and when TF=0, there is no single-step mode of debugging therefore, the trap is off.
- The interrupt flag(IF):- If the user sets IF=1, the CPU will recognize the external interrupt request i.e. Interrupt will be enabled. If the user sets IF=0, Interrput will be disabled.
- The direction flag (DF):- This bit is specifically used for string instructions. In that, we use source Index(SI) and destination Index(DI) as offset registers to point source area and destination area respectively. DF flags control the direction of SI and DI pointers.
- If DF=1, the string Instruction will automatically decrement the pointer from high address to low address
- If DF=0, The string instruction will automatically increment the pointer from the lower address to a higher address
Features of 8086 microprocessor
- 8086 has a 20-bit address bus that can access up to 2^20 memory locations (1 MB).
- It was the first 16-bit processor to have 16-bit ALU, 16-bit registers, an internal data bus, and a 16-bit external data bus resulting in faster processing.
- It has 256 vectored interrupts. There are also non-vectored interrupts in 8086.
- It has 14, 16-bit registers.
- It has a powerful instruction set, that supports multiply and divide operations also.
- 8086 can perform operations on bit, byte, word, or string types of data.
- It is available in 3 versions based on the frequency of operation
- 8086 → 5MHz
- 8086-2 → 8MHz
- 8086-1 → 10 MHz
- The 8086 can generate a 16-bit I/O address; hence it can access 2^16 = I/O ports. It can support up to 64K I/O ports. It provides 16-bit registers.
- It uses a memory banking system ie the entire data is not stored sequentially in a single memory of 1 MB but the memory is divided into 2 Banks of 512KB each. The banks are called Lower Banks (Even Banks) and Higher Banks (or Odd Banks).
- It uses a 2-stage pipelining i.e. Fetch stage, pre-fetches up to 6 bytes of instructions and stores them in the queue and the Execute stage, executes these instructions.